1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a skew detection circuit measuring a skew between a clock signal and a data strobe signal.
2. Description of Related Art
Transmission and reception of read data and write data between a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a memory controller may be performed synchronously with a data strobe signal. For example, in a write operation, a memory controller supplies a data strobe signal and write data to a semiconductor memory device, and the semiconductor memory device fetches the write data synchronously with the data strobe signal.
However, the write data fetched by the semiconductor memory device is transferred to a memory cell array synchronously with a clock signal, which is different from the data strobe signal. Therefore, when a skew exists between the data strobe signal and the clock signal, a write operation may not be performed correctly. To solve this problem, semiconductor memory devices often include a write leveling mode for measuring the skew between a clock signal and a data strobe signal (see Japanese Patent Application Laid-Open No. 2010-192030).
Upon entering a write leveling mode, a semiconductor memory device samples a clock signal at a timing of a rising edge of a data strobe signal supplied from a memory controller, and outputs the sampled clock signal from a data terminal. With this configuration, the memory controller can acquire an amount of skew between the data strobe signal and the clock signal. Consequently, the memory controller can adjust an output timing of the data strobe signal by taking the amount into consideration.
A semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 2010-192030 includes a DLL (Delay Locked Loop) circuit, which generates an internal clock signal that is phase-controlled. The read data are output in synchronism with the phase-controlled internal clock signal. However, the DLL circuit is a circuit block that consumes a relatively large amount of power. Therefore, the DLL circuit may not be provided in a semiconductor memory device for which low power consumption is required. In such a semiconductor memory device, read data which is parallel-to-serial converted by using an internal clock signal that is not phase controlled, and the read data is output to the outside without being phase-controlled. Even during a writing operation, the write data that have been input in synchronism with a data strobe signal are serial to parallel converted by using an internal clock signal that is not phase-controlled (See Japanese Patent Application Laid-Open No. 2011-108300). The parallel-to-serial conversion and the serial-to-parallel conversion are performed by using a plurality of frequency-divided clock signals, the phases of which are different from each other.
However, during the write leveling operation, the clock signal used needs to have the same frequency as an external clock signal, and the frequency-divided clock signals cannot be used. Therefore, in a semiconductor memory device having no DLL circuit, a plurality of frequency-divided clock signals are combined by a multiplier circuit, thereby reproducing an internal clock signal having the same frequency as the external clock signal. The internal clock signal needs to be used to perform the write leveling operation. Japanese Patent Application Laid-Open No. 2000-278103 discloses one example of the frequency dividing circuit and multiplier circuit.
However, if the internal clock signal is generated by the multiplier circuit, the delay caused by the multiplier circuit would be superimposed on the internal clock signal. As a result, the write leveling operation cannot be performed accurately. Such a phenomenon is not limited to the semiconductor memory devices such as DRAM. The phenomenon can occur in all semiconductor devices that transfer the write data using a plurality of frequency-divided clock signals and can perform the write leveling operation.